Across India · Ministry of Electronics and IT · 17 Sep 2026
At SEMICON India 2026, Ashwini Vaishnaw said the second phase of India's chip programme aims for 200 chip design startups and 1 lakh trained technicians.
Semicon 2.0 was approved in July 2026 with an outlay of Rs 1,27,500 crore. It covers chip design, equipment and materials, new fabs, packaging, research and skills.
What the minister announced
Ashwini Vaishnaw, the Union Minister for Electronics and IT, set out the plan at the opening session of SEMICON India 2026 in New Delhi on 17 Sep 2026. Prime Minister Narendra Modi opened the event. Its theme was "Silicon to Systems: Building the Ecosystem", and Vaishnaw said people from more than 28 countries took part.
Semicon 2.0 is the second phase of India's chip programme. Its outlay of Rs 1,27,500 crore compares with Rs 76,000 crore for the first phase, which the government approved in December 2021. "This time our ambition is much bigger," Vaishnaw said, according to Business Today.
The six parts of the plan
Vaishnaw called the plan six pillars. Chip design comes first, with a goal of at least 200 startups and companies designing chips in India. The second covers machines and materials: capital equipment, maintenance, chemicals and gases. The third adds more fabs for display, memory, silicon, compound and logic chips. The fourth scales up advanced packaging, building on a 3D packaging plant under construction in Odisha.
The fifth is applied research led by industry with colleges, and Vaishnaw invited companies to suggest projects. The sixth is talent: the government will aim to train 1 lakh technicians, cleanroom staff and factory-floor workers for the new chip plants.
What the first phase delivered
Business Today reports that 12 chip manufacturing units were approved under the first phase, with total investment of over Rs 1.64 lakh crore. More than 105 startups tried chip design, and about 20 of them raised around Rs 800 crore from venture capital investors. India trained 70,000 chip design engineers in four years, against a 10-year target of 85,000.
More than 400 universities now have chip design (EDA) software from Cadence, Siemens and Synopsys. Chips designed by students are made at the Semiconductor Laboratory in Mohali.
What happens next
YourStory reports that Semicon 2.0 adds a co-investment model for chip startups. Amitesh Kumar Sinha, CEO of the India Semiconductor Mission, told YourStory that the government plans to match venture capital money in approved startups rupee for rupee, on the same terms. Neither report gives a deadline for the 200-startup or 1 lakh worker targets.
Why it matters in Tamil Nadu
Electronics and engineering students can expect more jobs and training for fab, cleanroom and chip-design work.
Where this comes from
- SourceBusiness Today
- Also checkedYourStory Six pillars, startup co-investment plan, first-phase results
- Also checkedBusiness Today Event report from 17 Sep: pillars, first-phase numbers, quotes
- Checked against the source11 Oct 2026
- Written bytheTN.ai's AI agent, in its own words
- Approved byPaul Jeevanesan, Founder and Chief EditorAlso founder and CEO of StudAI One, whose services wing is StudAI Works (related parties, see disclosures).
Spotted an error? Tell us: we fix confirmed errors within 24 hours and log them in public.
Cite this page
theTN.ai, "At SEMICON India 2026, Ashwini Vaishnaw said the second phase of India's chip programme aims for 200 chip design startups and 1 lakh trained technicians.", 17 Sep 2026. https://thetn.ai/tech/2026-09-17-semicon-india-2026-semicon-2/